1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device allowing fast sensing. More particularly, the invention relates to a semiconductor memory device of a shared sense amplifier structure, which can perform fast sensing operation to allow fast access to sense amplifiers.
2. Description of the Background Art
FIG. 30 shows a shared sense amplifier structure in the prior art. In FIG. 30, a sense amplifier SA is arranged between bit lines BLL and /BLL included in a memory sub-block MAL and bit lines BLR and /BLR included in a memory sub-block MAR. Bit lines BLL and /BLL as well as bit lines BLR and /BLR are coupled to sense amplifier SA via bit line isolating gates BIGL and BIGR, respectively. These bit lines BLL and BLR as well as complementary bit lines /BLL and /BLR are equivalent to divided bit lines of bit lines BL and /BL. Sense amplifier SA is arranged in a substantially central position between these bit lines BLL and BLR and between bit lines /BLL and /BLR.
Sense amplifier SA includes an n-channel MOS transistor Q1 having conduction nodes connected to bit line BL and a common source node S2N, respectively, and a gate coupled to complementary bit line /BL, an n-channel MOS transistor Q2 having conduction nodes connected to complementary bit line /BL and common source node S2N, respectively, and a gate connected to bit line BL, a p-channel MOS transistor Q3 having conduction nodes connected to bit line BL and common source node S2P, respectively, and a gate connected to complementary bit line /BL, and a p-channel MOS transistor Q4 having conduction nodes connected to complementary bit line /BL and common source node S2P, respectively, and a gate connected to bit line BL.
MOS transistors Q1 and Q2 are cross-coupled, and discharge a lower potential bit line of bit lines BL and /BL when made active. MOS transistors Q3 and Q4 are cross-coupled, and charges a higher potential bit line of bit lines BL and /BL when made active. For activating sense amplifier SA, an n-channel MOS transistor Q5 which is turned on in response to activation of a sense amplifier activating signal .phi.SON to connect common source node S2N to a source ground line SGD, and a p-channel MOS transistor Q6 which is turned on in response to activation of a sense amplifier activating signal .phi.SOP to connect common source node S2P to a source power supply line SVC are provided.
Bit line isolating gate BIGL includes transfer gates TX1 and TX2 formed of n-channel MOS transistors, and is made conductive when a bit line isolation instructing signal .phi.SHRL is active (at L-level), to isolate bit lines BLL and /BLL from bit lines BL and /BL (sense nodes), respectively. Bit line isolating gate BIGR likewise includes transfer gates T3 and T4 formed of n-channel MOS transistors, and is made conductive when a bit line isolation instructing signal .phi.SHRR is active (L-level), to isolate bit lines BL and /BL from bit lines BLR and /BLR, respectively.
For bit lines BL and /BL, an equalize circuit BEQ for equalizing bit lines BL and /BL (BLL, BLR, /BLL and /BLR) to a predetermined potential VBL during standby, and a column select gate CSG for connecting bit lines BL and /BL to internal data lines I/O and ZI/O in accordance with a column select signal YS on a column select line CSL received from a column decoder (not shown), respectively are further provided.
Equalize circuit BEQ includes an n-channel MOS transistor Q7 which is turned on in response to activation of an equalize instructing signal .phi.EQ to electrically short-circuit bit lines BL and /BL, and n-channel MOS transistors Q8 and Q9 which transmit a predetermined voltage (intermediate voltage) VBL onto bit lines BL and /BL in response to activation of equalize instructing signal .phi.EQ, respectively.
Column select gate CSG includes n-channel MOS transistors Q10 and Q11 which are turned on in response to activation of column select signal YS, to connect bit lines BL and /BL to internal data lines I/O and ZI/O, respectively. In a standby cycle, bit line isolation instructing signals .phi.SHRL and .phi.SHRR are at H-level so that bit lines BLL and BLR are connected to bit line BL, and bit lines /BLL and /BLR are connected to bit line /BL. In the standby cycle, bit line equalize instructing signal BEQ is active, and these bit lines BL, BL, BLR, /BL, BL and /BLR are equalized to intermediate voltage VBL.
Generally, common source nodes S2N and S2P of sense amplifier SA are commonly used by a plurality of sense amplifiers, and are equalized to the intermediate voltage level.
In memory sub-blocks MAL and MAR, word lines are arranged in the direction crossing bit lines BLL and /BLL as well as bit lines BLR and /BLR. Memory cells are arranged corresponding to the crossings between word lines and bit lines. In a dynamic type semiconductor memory device, the memory cell has a memory cell structure of one-transistor/one-capacitor type. Operation of the shared sense amplifier shown in FIG. 30 will now be described with reference to signal waveforms shown in FIG. 31.
In the standby cycle, bit line equalize instructing signal .phi.EQ is at H-level so that equalize circuit BEQ is activated to equalize bit lines BL and /BL to the level of intermediate voltage VBL. At this time, bit line equalize instructing signals .phi.SHRL and .phi.SHRR are at H-level of a high voltage Vpp, and bit line isolating gates BIGL and BIGR are on, so that intermediate voltage VBL of equalize circuit BEQ is transmitted onto bit lines BLL and /BLL as well as BLR and /BLR. In memory sub-blocks MAL and MAR, the bit lines are precharged to the intermediate voltage level. Sense amplifier activating signals .phi.SON and .phi.SOP are inactive, and therefore sense amplifier SA is inactive.
When a memory cycle starts, bit line equalize instructing signal .phi.EQ first attains the inactive state at L-level, and deactivates equalize circuit BEQ. Then, an operation of selecting a memory sub-block is performed in accordance with an address signal (not shown). It is now assumed that a word line (WL) included in memory sub-block MAR is selected. In this state, bit line isolation instructing signal .phi.SHRL attains the active state at L-level, and bit line isolating gate BIGL is turned off so that bit lines BLL and /BLL are isolated from bit lines BL and /BL. The other bit line isolation instructing signal .phi.SHRR is held at high voltage Vpp as in the standby cycle, and bit lines BLR and /BLR are continuously connected to bit lines BL and /BL, respectively.
Then, row selection is performed in accordance with the address signal. In memory sub-block MAR, selected word line WL is driven to the selected state, and the voltage level thereof rises to high voltage Vpp level. The data of the memory cells connected to selected word line WL are read onto the corresponding bit lines, and the voltage levels on bit lines BL and /BL change in accordance with the read memory cell data. More specifically, one of paired bit lines BL and /BL is connected to a memory cell, and has the voltage level changed in accordance with the memory cell data. The other bit line maintains the precharge voltage level. FIG. 31 shows signal waveforms in the operation where memory cell data at H-level is read onto bit line BL.
When a voltage difference between bit lines BL and /BL sufficiently increases, sense amplifier activating signals .phi.SON and .phi.SOP are activated so that MOS transistors Q5 and Q6 for sense amplifier activation are turned on to activate sense amplifier SA. Since the voltage level on bit line /BL is lower than that on bit line BL, MOS transistors Q1 and Q2 discharge the voltage level of bit line /BL to the ground voltage GND level. The other bit line BL is charged to power supply voltage Vccc level by MOS transistors Q3 and Q4.
After the voltage levels on bit lines BL and /BL are stabilized at power supply voltage Vccc level and ground voltage GND level, respectively, column selection for data access is performed. FIG. 31 shows the operation, in which column selecting operation is successively performed, and the column select signal on column select line CSL successively changes. Column select gate CSG is turned on in accordance with column select signal YS on column select line CSL, and bit lines BL and /BL are connected to internal data lines I/O and ZI/O, respectively, so that data amplified and latched by sense amplifier SA is transmitted onto internal data lines I/O and ZI/O. Then, write/read of data for the selected sense amplifier is performed.
When the memory cycle is completed, word line WL is first driven to the unselected state, and then sense amplifier activating signals .phi.SON and .phi.SOP are driven to the inactive state. Equalize instructing signal .phi.EQ returns to H-level, and bit line isolation instructing signal .phi.SHRL returns to the inactive state at H-level (high voltage Vpp level). Thereby, bit lines BL and /BL return to the initial level, i.e., intermediate voltage VBL level.
In the shared sense amplifier structure shown in FIG. 30, sense amplifier SA is arranged in a central position between bit lines BLL and BLR as well as between /BLL and /BLR. Sense amplifier SA is connected to bit line pair BLR and /BLR or bit line pair BLL and /BLL for performing the sensing operation. Thus, sense amplifier SA is connected only to a half of all the bit lines (BL and /BL) in the sensing operation so that the load to be driven by the sense amplifier is reduced, and the sensing operation can be performed fast. Bit line isolation instructing signals .phi.SHRR and .phi.SHRL are held at high voltage Vpp level when they are inactive. Thereby, the data sensed and amplified by sense amplifier SA can be restored into the original memory cell without a threshold voltage loss across the transfer gate in the bit line isolating gate.
The above operation sequence of the shared sense amplifier structure in the prior art cannot fully satisfy the demands of the semiconductor memory devices in recent years, i.e., the demands for fast operation, large storage capacity and low power consumption. This will now be described.
With increase in storage capacity, components are miniaturized to a higher extent. For ensuring the reliability of components thus miniaturized and reducing the power consumption, a lower power supply voltage is used. Particularly in memory cells, a voltage of an array power supply (sense amplifier power supply) is lowered for ensuring the reliability of the memory cells. As shown in FIG. 32, the memory cell includes a capacitor MQ for storing information, and an access transistor MT for connecting memory cell capacitor MQ to corresponding bit line BL (or /BL) in response to the signal voltage on word line WL. Access transistor MT is formed of an n-channel MOS transistor (insulated gate field effect transistor). In a miniaturizing process, with reduction in size of access transistors MT, a gate insulating film of access transistor MT is reduced in accordance with a predetermined scaling rule for improving on/off controllability by the voltage on the gate electrode of access transistor MT. If access transistor MT has the gate insulating film reduced in thickness, the voltage level of high voltage Vpp which can be applied to word line WL is restricted for preventing dielectric breakdown of the gate insulating film of access transistor MT. Thus, the voltage level of voltage Vpp at H-level on word line WL must be lowered in accordance with miniaturization of the components. When H-level data is to be written into memory cell MC, consideration must be given to the level of voltage Vpp on word line WL and a loss due to the threshold voltage of access transistor MT. Thus, the voltage level on bit line BL is set to Vpp-Vth, where Vth represents the threshold voltage of access transistor MT. Bit line BL is driven by sense amplifier SA. Therefore, the level of voltage Vccc at H-level driven by sense amplifier SA naturally lowers as the voltage level of voltage Vpp at H-level on word line WL lowers.
For reducing the power consumption, charging/discharging currents of sense amplifier SA are to be reduced, and therefore the voltage level of sense amplifier power supply voltage Vccc is lowered. Sense amplifier SA is formed of MOS transistors, and the charging/discharging speed thereof depends on the gate-source voltage. Accordingly, when sense amplifier power supply voltage Vccc lowers, the operation speed of sense amplifier SA lowers and the sensing time increases so that the bit line voltage is made definite at a delayed or slower timing, and the access time increases.
Miniaturization of components results in reduction in pitch of bit lines and increase in parasitic capacitance between bit lines, and also results in increase in parasitic capacitance between a bit line and a signal line which is connected to a gate of a MOS transistor connected to the bit line. Accordingly, the load to be driven by sense amplifier SA increases, and the speed of sensing operation decreases.
For increasing the storage capacity and increasing a cell occupying rate to the array area, the length of bit line is increased, and the number of memory cells connected to each bit line is increased. Thereby, the number of regions of sense amplifier bands (i.e., regions where the sense amplifiers are arranged) is reduced to half, and the chip area is reduced. For example, in 64-Mbit DRAMs at the present time, 128 memory cells are connected to each bit line. However, 256 memory cells are connected to each bit line in 64-Mbit DRAM of the next generation and 256-Mbit DRAM. Each bit line is driven by one sense amplifier SA. As the bit line capacitance increases with increase in number of memory cells, the load to be driven by the sense amplifier increases, and the speed of sensing operation decreases.
The foregoing reduction in sensing operation speed results in delay in access for reading/writing data (because of delay in start of the column selection), and therefore lowers the performance of the memory device.
As the storage capacity increases, the length of internal data lines increases, and the interconnection line capacitance thereof increases. The internal data lines are connected to main amplifiers (not shown). In the data read operation, sense amplifier SA drives the internal data line, and the sense amplifier data is transmitted to the main amplifier. Accordingly, with increase in interconnection line capacitance of the internal data line, delay in data transmission from sense amplifier SA to main amplifier MA increases so that fast data reading cannot be implemented. In the data write operation, and particularly when a write driver drives the internal data line for writing the data into the sense amplifier, delay likewise occurs in data signal transmission from the write driver to the sense amplifier, and fast access cannot be achieved. Since the write driver is required to drive a large parasitic capacitance of the sense amplifier, a long time is required for data writing.